Freescale Semiconductor
Data Sheet
Document Number: MPC8610EC
Rev. 0, 10/2008
MPC8610 Integrated Host Processor
Hardware Specifications
Features
• High-performance, 32-bit e600 core, that implements the
Power Architecture™ technology
– Eleven execution units and three register files
– Two separate 32-Kbyte instruction and data level 1 (L1)
caches
– Integrated 256-Kbyte, eight-way set-associative unified
instruction and data level 2 (L2) cache with ECC
– 36-bit real addressing
– Multiprocessing support features
– Power and thermal management
• MPX coherency module (MCM)
• Address translation and mapping units (ATMUs)
• DDR/DDR2 memory controller
– 64- or 32-bit data path (72-bit with ECC)
– Up to 533-MHz DDR2 data rate and up to 400 MHz
DDR data rate
– Up to 16 Gbytes memory
• Enhanced local bus controller (eLBC)
– Operating at up to 133 MHz
– Eight chip selects
• Display interface unit
– Maximum display resolution: 1280
× 1024
– Maximum display refresh rate: 60 Hz
– Display color depth: up to 24 bpp
– Display interface: parallel TTL
• OpenPIC-compliant programmable interrupt controller
(PIC)
– Supports 16 programmable interrupt and processor task
priority levels
– Supports 12 discrete external interrupts and 48 internal
interrupts
– Eight global high resolution timers/counters that can
generate interrupts
– Support for PCI Express message-shared interrupts
(MSIs)
• Dual I
2
C controllers
– Master or slave I
2
C mode support
– Boot sequencer
– Optionally loads configuration data from serial ROM at
reset via I
2
C interface
– Can be used to initialize configuration registers and/or
memory
– Supports extended I
2
C addressing mode
DUART
Fast InfraRed interface
Serial peripheral interface
– Master or slave support
Dual integrated four-channel DMA controllers
– All channels accessible by both local and remote masters
– Supports transfers to or from any local memory or I/O
port
– Ability to start and flow control each DMA channel
from external 3-pin interface
Watchdog timer
Dual global timer modules
32-bit PCI interface, 33 or 66 MHz bus frequency
Dual PCI Express® controllers
– PCI Express 1.0a compatible
– PCI Express controller 1 supports x1, x2, and x4 link
widths; PCI Express controller 2 supports x1, x2, x4, and
x8 link widths
– 2.5 Gbaud, 2.0 Gbps lane
Device performance monitor
– Supports eight 32-bit counters that count the occurrence
of selected events
– Ability to count up to 512 counter-specific events
– Supports 64 reference events that can be counted on any
of the 8 counters
– Supports duration and quantity threshold counting
– Burstiness feature that permits counting of burst events
with a programmable time between bursts
– Triggering and chaining capability
– Ability to generate an interrupt on overflow
IEEE Std 1149.1™ compliant, JTAG boundary scan
Available as 783-pin, flip-chip, plastic ball grid array
(FC-PBGA)
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© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4
1.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .16
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.6 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . .26
2.7 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.8 Display Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.9 I
2
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI). . . . . . . . . . .44
2.12 Synchronous Serial Interface (SSI). . . . . . . . . . . . . . . .44
2.13 Global Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . .48
2.14 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.15 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . .50
2.16 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.17 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .54
2.18 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3
2.19 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . .
3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Power Supply Design and Sequencing . . . . . . . . . . . .
3.3 Decoupling Recommendations . . . . . . . . . . . . . . . . . .
3.4 SerDes Block Power Supply Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Connection Recommendations . . . . . . . . . . . . . . . . . .
3.6 Pull-Up and Pull-Down Resistor Requirements . . . . . .
3.7 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . .
3.8 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . .
3.9 JTAG Configuration Signals. . . . . . . . . . . . . . . . . . . . .
3.10 Guidelines for High-Speed Interface Termination . . . .
3.11 Guidelines for PCI Interface Termination . . . . . . . . . . .
3.12 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
72
72
76
77
77
77
78
78
79
79
82
83
84
90
92
93
94
4
5
6
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0
2
Freescale Semiconductor
Figure 1
shows the major functional units within the MPC8610.
MPC8610
e600 Core Block
e600 Core w/ AltiVec
32-Kbyte
L1 Instruction Cache
32-Kbyte
L1 Data Cache
MPX Bus
MPX Coherency Module (MCM)
DDR/DDR2
SDRAM Controller
Local Bus Controller
(eLBC)
PCI Express
x1,x2,x4
PCI Express
Interface 1 (×4)
OCeaN
Switch
Fabric 1
Display Interface Unit
Programmable Interrupt
Controller
(PIC)
2 x I
2
C Controller
External
Control
Four-Channel
DMA Controller 1
2 x Dual Universal
Asynchronous
Receiver/Transmitter
(DUART)
2 x Fast/Serial
Infra-Red Interface
(FIRI/SIRI)
PCI Express
x1,x2,x4,x8
PCI Express
Interface 2 (×8)
OCeaN
Switch
Fabric 2
Serial Peripheral
Interface
2 x Global Timer Module
2 x Synchronous Serial
Interface (SSI)
DDR/DDR2
SDRAM
ROM, NAND Flash,
NOR Flash, GPIO
LCD
256-Kbyte
L2
Cache
IRQs
I
2
C
32-Bit PCI
32-Bit PCI
Interface
Serial
IrDA
SPI
Peripherals
Timer
Control
I
2
S/AC97 Audio
External
Control
Four-Channel
DMA Controller 2
Figure 1. MPC8610 Block Diagram
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
3
Pin Assignments and Reset States
1
1.1
Pin Assignments and Reset States
Pin Assignments
Table 1. Signal Reference by Functional Block
Name
1
Package Pin Number
Clocking Signals
4
Pin Type
Power Supply
Notes
Table 1
provides the pin assignments for the signals.
SYSCLK
RTC
D28
A25
DDR Memory Interface Signals
2
I
I
OV
DD
OV
DD
17
MA[15:0]
AH28, AH25, AH6, AH24, AH22, AG13,
AG22, AG19, AH21, AH19, AH18, AG16,
AH16, AG15, AH15, AH14
AG25, AH13, AH12
AH10, AG7, AH9, AG4
W26, Y26, AB24, AC28, W27, Y28, AB27,
AB26 AD27, AE27, AD25, AF25, AC26,
AD28, AC25, AD24, AG24, AF23, AE21,
AG21, AE24, AE23, AF22, AD21, AH20,
AC19, AG18, AF17, AE20, AF20, AE18,
AC17, AC13, AD12, AG9, AE9, AD13,
AE12, AD10, AC10, AF8, AE8, AD6, AH5,
AD9, AH8, AG6, AE6, AF4, AD4, AC3, AC1,
AF5, AE5, AD2, AC4, AB1, AB2, Y1, Y6,
AB6, AA6, Y3, Y4
AD16, AF16, AC15, AF15, AH17, AE17,
AA15, AB15
Y25, AE26, AH23, AD19, AF11, AF7, AE3,
AB4, AC16
AA25, AF26, AD22, AD18, AF10, AC7, AD3,
AA5, Y15
AA27, AF28, AC22, AF19, AE11, AD7, AE2,
AB5, AB16
AG10
AH11
AG12
AF14, AG28, AH3, AD15, AH27, AG2
AF13, AG27, AH2, AD14, AH26, AG1
AB28, AA28, AE28, W28
AD1, AE1
O
GV
DD
MBA[2:0]
MCS[0:3]
MDQ[0:63]
O
O
I/O
GV
DD
GV
DD
GV
DD
MECC[0:7]
MDM[0:8]
MDQS[0:8]
MDQS[0:8]
MCAS
MWE
MRAS
MCK[0:5]
MCK[0:5]
MCKE[0:3]
MDIC[0:1]
I/O
O
I/O
I/O
O
O
O
O
O
O
I/O
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
18
19
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0
4
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. Signal Reference by Functional Block (continued)
Name
1
MODT[0:3]
Package Pin Number
AH7, AH4, AG3, AF1
Enhanced Local Bus Signals
4
LAD[0:31]
AA21, AA22, AA23, Y21, Y22, Y23, Y24,
W23, W24, W25, V28, V27, V25, V23, V21,
W22, U28, U26, U24, U22, U23, U20, U21,
W20, V20, T24, T25, T27, T26, T21, T22,
T23
N28, M28, L28, P25
P19
M27
U18
P28
R18
R19
R20
M18
N18
N27
P20
P21
M19, M21, M22, M23, N23, N24, M26, N20,
N21, N22
R24, R22, P23, P24, P27
R23
N26
R26
T19
T20
W19
T18
T28
R28
L19
L20
L21
I/O
BV
DD
20
Pin Type
O
Power Supply
GV
DD
Notes
LDP[0:3]/LA[6:9]
LA10/SSI1_TXD
LA11/SSI1_TFS
LA12/SSI1_TCK
LA13/SSI1_RCK
LA14/SSI1_RFS
LA15/SSI1_RXD
LA16/SSI2_TXD
LA17/SSI2_TFS
LA18/SSI2_TCK
LA19/SSI2_RCK
LA20/SSI2_RFS
LA21/SSI2_RXD
LA[22:31]
LCS[0:4]
LCS5/DMA2_DREQ0
LCS6/DMA2_DACK0
LCS7/DMA2_DDONE0
LWE0/LFWE/LBS0
LWE1/LBS1
LWE2/LBS2
LWE3/LBS3
LBCTL
LALE
LGPL0/LFCLE
LGPL1/LFALE
LGPL2/LOE/LFRE
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
BV
DD
20, 23
23
23
23
23
23
23
23
23
23
23
23
20
21
21, 22, 23
21, 23
21, 23
20
20
20
20
20
20
20
20
20
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
5
